
reg [11:0] data_buf;
reg [2 :0] cnt;

always @(posedge clk or negedge rst_n) begin : buf_ctrl
	if(~rst_n) data_buf <= 12'b0;
	else if(vld_in) data_buf <= {data_buf[5:0], data_in};
end

always @(posedge clk or negedge rst_n) begin : cnt_ctrl
	if(~rst_n) cnt <= 3'd0;
	else if(vld_in) cnt <= cnt + 3'd1;
	else if(cnt == 3'd4) cnt <= 3'd1;
end

always @(posedge clk or negedge rst_n) begin : out_ctrl
	if(~rst_n) data_out <= 8'b0;
	else begin
		case (cnt)
			3'd0 :begin
				data_out <= 8'b0;
				vld_out <= 1'b0;
			end
			3'd1 :begin
				data_out <= 8'b0;
				vld_out <= 1'b0;
			end
			3'd2 :begin
				data_out <= data_buf[7:0];
				vld_out <= 1'b1;
			end
			3'd3 :begin
				data_out <= data_buf[9:2];
				vld_out <= 1'b1;
			end
			3'd4 :begin
				data_out <= data_buf[11:4];
				vld_out <= 1'b1;
			end
			default :begin
				data_out <= 8'b0;
				vld_out <= 1'b0;
			end
		endcase
	end
end